1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to a low power memory controller embodied upon an integrated circuit for selectively controlling either a single data rate (SDR) synchronous dynamic random access memory (SDRAM) or a double data rate (DDR) DRAM.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
There are numerous types of memories available in the marketplace. For example, large volumes of data can be stored in magnetic memory, such as a hard disk drive. Lesser quantities of data can be stored in memory arranged upon an integrated circuit, oftentimes referred to as “semiconductor memory.” Semiconductor memory is typically arranged closer to the core logic unit or execution unit (oftentimes referred to as the “execution engine”) than the hard disk drive, and can be accessed much faster than the disk drive.
Common to semiconductor memory is an array of storage cells. Depending on the function of the semiconductor memory, each storage cell can have a significantly different architecture and function. For example, semiconductor memory can be volatile or non-volatile. Types of volatile memory include memory that must be periodically refreshed (DRAMs) or memory that will lose its programmed state if power is removed (SRAMs).
The differences between SRAMs and DRAMs are fairly significant. For example, each cell of SRAM includes latch and pass transistors. Conversely, each cell of DRAM involves simply one transistor. While DRAMs are significantly denser than SRAMs, DRAMs require additional support circuitry to coordinate the access of each cell, along with the need to periodically refresh that cell. Since SRAMs typically have faster access times than DRAMs, SRAMs are oftentimes used as the primary cache of the microprocessor or execution unit. DRAMs, on the other hand, are generally used as the main semiconductor memory and are controlled by a memory controller linked to the execution engine typically by a memory bus or system bus. Each transaction between the execution engine and the memory involves a particular bus cycle.
There are numerous types of DRAMs, some of which are: fast page mode DRAMs, extended data out DRAMs, burst extended data out DRAMs, and the more recent synchronous DRAMs (or SDRAMs). Unlike DRAMs, SDRAMs take advantage of the fact that memory accesses by the execution unit are typically sequential. SDRAMs are designed to fetch all bits within a particular burst in sequential fashion by allowing the column address to be incremented sequentially and in sync with the system clock of the execution engine or processor. This allows an SDRAM one important advantage over other forms of asynchronous DRAMs: data transfer delivery from the SDRAM at burst rates exceeding, for example, 100 MHz.
Along with a decrease in access time of the SDRAM came yet another enhancement. Instead of providing source-synchronous data capture at the clock frequency, double data rate (DDR) SDRAM allows data to be captured at a rate of twice the clock frequency. This is accomplished by utilizing a 2n-prefetch architecture, where the internal data bus of the DDR SDRAM is twice the “n” width of the external data bus to allow data capture of twice per system clock cycle. Details of the difference between a single data rate (SDR) SDRAM and DDR SDRAM are set forth in “General DDR SDRAM Functionality,” Micron Technology 2001 (herein incorporated by reference).
While both SDR and DDR memory devices include the same core memory array of cells, the input/output (I/O) interface is considerably different. For example, DDR utilizes a differential pair of system clock signals (CK and #CK) to formulate the triggering rising and falling clock edges, and data strobe (DQS) signals are needed to drive the data signal (DQ) to and from the DDR-accessed memory banks. In addition to its double data rate operation, DDR DRAMs often use memory banks that operate similar to virtual channels. The size of the memory bank can vary and, depending on the overall capacity of the memory module, a memory bank can possibly include an entire semiconductor memory device.
Most modern semiconductor memory units are configured as a memory module, with multiple DRAMs placed upon a printed circuit board (PCB). The DRAMs can be configured in a single line or in two lines to form a single inline memory module (SIMM) or a dual inline memory module (DIMM). The SIMM or DIMM unit is readily replaceable since it typically employs edge connectors that slide into a bus receptacle.
In order to control the memory module that can utilize two or more banks of memory arrays for interleaved operations, a memory controller is needed. In many applications, the memory controller is embodied on the same integrated circuit as the execution engine. The combination of execution engine and memory controller can be formed as an application specific integrated circuit (ASIC) or as a programmable logic unit, such as a gate array or programmable logic array (PLA).
As the price and market demand for semiconductor memory changes, it is desirable to be able to change out the semiconductor memory for the cheaper or higher-performing type of memory. However, it is typically difficult to easily modify the memory controller to accommodate, for example, SDRAM instead of DRAM. For example, a user might want to replace SDR SDRAM with faster DDR DRAM, or DDR SDRAM. As the market demand for higher speed DDR increases, the costs associated with making DDR on a per-byte basis might also steadily decline compared to the SDR counterpart. However, depending on the availability of SDR versus DDR, it would be desirable to employ a memory controller that can accommodate either. Yet, existing memory controllers formed on an integrated circuit with an execution engine cannot be readily adapted to either forms of memory, either because the memory controller is fixed in its ASIC design or the functionality of the memory controller suited for SDR cannot be readily modified to accommodate, for example, the DQS signals and latching on both the rising and falling clock edges. As the market for DRAMs constantly evolves, a need exists for a memory controller that can accommodate SDR or DDR memory, such as SDR SDRAM or DDR DRAM without any modifications to the memory controller hardware.